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Rev 1; 11/03
3.3V Spread-Spectrum EconOscillator
General Description
The DS1087L is a clock generator that produces a spread-spectrum (dithered) square-wave output of frequencies from 130kHz to 66.6MHz. The DS1087L is shipped from the factory programmed at a specific frequency and spread-spectrum percentage. The user still has access to an internal frequency divider, selectable 2% or 4% dithered output, and programmable output power-down/disable mode through a 2-wire programming interface. All the device settings are stored in nonvolatile (NV) EEPROM allowing it to operate in stand-alone applications. The DS1087L has powerdown and output-enable control pins for power-sensitive applications.
Features
Factory Programmed Square-Wave Generator from 130kHz to 66.6MHz No External Timing Components Required EMI Reduction 2.7V to 3.6V Supply User Programmable Down to 130kHz with Divider (Dependent on Master Oscillator Frequency) 2% or 4% Selectable Dithered Output Glitchless Output-Enable Control 2-Wire Serial Interface Nonvolatile Settings Power-Down Mode Programmable Output Power-Down/Disable Mode
DS1087L
Applications
Printers Copiers PCs Computer Peripherals Cell Phones Cable Modems
Ordering Information
PART DS1087LU-yxx TEMP RANGE -40C to +85C PIN-PACKAGE 8 SOP (118 mils)
Standard Frequency Options
PART DS1087LU-202 DS1087LU-402 DS1087LU-210 DS1087LU-216 DS1087LU-266 DS1087LU-466 DS1087LU-yxx FREQUENCY (MHz) 2.0480 2.0480 10.0 16.6 66.6 66.6 Fixed up to 66.6 SPREAD (%) 2 4 2 2 2 4 2 or 4
SPRD VCC 2 OUT 1
Pin Configuration
TOP VIEW
8 7
SCL SDA PDN OE
DS1087L
3 6 5 GND 4
Custom frequencies and over 20 standard frequencies available, contact factory.
SOP (118 mils)
EconOscillator is a trademark of Dallas Semiconductor. Typical Operating Circuits appear at end of data sheet.
______________________________________________ Maxim Integrated Products
1
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3.3V Spread-Spectrum EconOscillator DS1087L
ABSOLUTE MAXIMUM RATINGS
Voltage Range on VCC Relative to Ground ..........-0.5V to +6.0V Voltage Range on SPRD, PDN, OE, SDA, SCL Relative to Ground* ................................-0.5V to (VCC + 0.5V) Operating Temperature Range ...........................-40C to +85C *This voltage must not exceed 6.0V. Programming Temperature Range .........................0C to +70C Storage Temperature Range .............................-55C to +125C Soldering Temperature ..................See IPC/JEDEC J-STD-020A
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
(VCC = 2.7V to 3.6V, TA = -40C to +85C.)
PARAMETER Supply Voltage High-Level Input Voltage (SDA, SCL, SPRD, PDN, OE) Low-Level Input Voltage (SDA, SCL, SPRD, PDN, OE) SYMBOL VCC VIH VIL (Note 1) CONDITION MIN 2.7 0.7 x VCC -0.3 TYP MAX 3.6 VCC + 0.3 0.3 x VCC UNITS V V V
DC ELECTRICAL CHARACTERISTICS
(VCC = 2.7V to 3.6V, TA = -40C to +85C.)
PARAMETER High-Level Output Voltage (OUT) Low-Level Output Voltage (OUT) Low-Level Output Voltage (SDA) High-Level Input Current Low-Level Input Current Supply Current (Active) Standby Current (Power-Down) SYMBOL VOH VOL VOL1 VOL2 IIH IIL ICC ICCQ IOL = 4mA 3mA sink current 6mA sink current VCC = 3.6V VIL = 0 CL = 15pF (output at f0) Power-down mode -1 15 5 0 0 CONDITION IOH = -4mA, VCC = min MIN 2.4 0.4 0.4 0.6 1 TYP MAX UNITS V V V A A mA A
2
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3.3V Spread-Spectrum EconOscillator
MASTER OSCILLATOR CHARACTERISTICS
(VCC = 2.7V to 3.6V, TA = -40C to +85C.)
PARAMETER Master Oscillator Range Available Master Oscillator Frequency Tolerance Voltage Frequency Variation Temperature Frequency Variation Temperature Frequency Variation Dither Frequency Range Dither Rate SYMBOL f0 f0 f0 fV f0 fT f0 fT f0 VCC = 3.3V, TA = +25C (Notes 2, 13) Over voltage range, TA = +25C (Note 3) 0C to +70C, VCC = 3.3V (Note 4) -40C to +85C, VCC = 3.3V (Note 4) Prescaler bit J0 = 1 (Note 5) Prescaler bit J0 = 0 (Note 5) CONDITION MIN 33.3 -0.5 -0.75 -0.5 -1.5 2 4 f0 / 4096 TYP MAX 66.6 +0.5 +0.75 +0.5 +0.5 UNITS MHz % % % % % Hz
DS1087L
AC ELECTRICAL CHARACTERISTICS
(VCC = 2.7V to 3.6V, TA = -40C to +85C.)
PARAMETER Frequency Stable After PRESCALER Change Power-Up Time Enable of OUT After Exiting Power-Down Mode OUT Disabled After Entering Power-Down Mode Load Capacitance Output Duty Cycle (OUT) tPOR + tSTAB tSTAB tPDN CL (Note 7) TA = +25C 45 15 (Note 6) 0.1 SYMBOL CONDITION MIN TYP MAX 1 0.5 500 1 50 55 UNITS period ms s ms pF %
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3.3V Spread-Spectrum EconOscillator DS1087L
AC ELECTRICAL CHARACTERISTICS--2-WIRE INTERFACE
(VCC = 2.7V to 3.6V, TA = 0C to +70C.)
PARAMETER SCL Clock Frequency Bus Free Time Between a STOP and START Condition Hold Time (repeated) START Condition LOW Period of SCL HIGH Period of SCL Setup Time for a Repeated START Data Hold Time Data Setup Time Rise Time of Both SDA and SCL Signals Fall Time of Both SDA and SCL Signals Setup Time for STOP Capacitive Load for Each Bus NV Write Cycle Time Input Capacitance SYMBOL fSCL tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO CB tWR CI 5 CONDITION Fast mode (Note 8) Standard mode (Note 8) Fast mode (Note 8) Standard mode (Note 8) Fast mode (Notes 8 and 9) Standard mode (Notes 8 and 9) Fast mode (Note 8) Standard mode (Note 8) Fast mode (Note 8) Standard mode (Note 8) Fast mode Standard mode Fast mode (Notes 8, 10, and 11) Standard mode (Notes 8, 10, and 11) Fast mode (Note 8) Standard mode (Note 8) Fast mode (Note 12) Standard mode (Note 12) Fast mode (Note 12) Standard mode (Note 12) Fast mode Standard mode (Note 12) 1.3 4.7 0.6 4.0 1.3 4.7 0.6 4.0 0.6 4.7 0 0 100 250 20 + 0.1CB 20 + 0.1CB 20 + 0.1CB 20 + 0.1CB 0.6 4.0 400 10 300 1000 300 1000 0.9 0.9 MIN TYP MAX 400 100 UNITS kHz s s s s s s ns ns ns s pF ms pF
NONVOLATILE MEMORY CHARACTERISTICS
(VCC = 2.7V to 3.6V)
PARAMETER Writes SYMBOL +70C CONDITION MIN 10,000 TYP MAX UNITS
4
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3.3V Spread-Spectrum EconOscillator DS1087L
Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: All voltages are referenced to ground. This is the absolute accuracy of the master oscillator frequency at the default settings. This is the change that is observed in master oscillator frequency with changes in voltage from nominal voltage at TA = +25C. This is the percentage frequency change from the +25C frequency due to temperature at VCC = 3.3V. The dither deviation of the master oscillator frequency is unidirectional and lower than the undithered frequency. This indicates the time elapsed between power-up and the output becoming active. An on-chip delay is intentionally introduced to allow the oscillator to stabilize. tstab is equivalent to approximately 512 master clock cycles and depends on the programmed master oscillator frequency. Output voltage swings may be impaired at high frequencies combined with high output loading. A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT > 250ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line at least tR MAX + tSU:DAT = 1000ns + 250ns = 1250ns before the SCL line is released. After this period, the first clock pulse is generated. A device must internally provide a hold time of at least 300ns for the SDA signal (referred to as the VIH MIN of the SCL signal) to bridge the undefined region of the falling edge of SCL. The maximum tHD:DAT need only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. CB--total capacitance of one bus line, timing referenced to 0.9 x VCC and 0.1 x VCC. Typical frequency shift due to aging is 0.5%. Aging stressing includes Level 1 moisture reflow preconditioning (24hr +125C bake, 168hr 85C/85%RH moisture soak, and 3 solder reflow passes +240 +0/-5C peak) followed by 1000hr max VCC biased 125C HTOL, 1000 temperature cycles at -55C to +125C, and 168hr 121C/2 ATM Steam/Unbiased Autoclave.
Note 7: Note 8:
Note 9: Note 10: Note 11: Note 12: Note 13:
Typical Operating Characteristics
(VCC = 3.3V, TA = +25C, unless otherwise noted.)
ACTIVE SUPPLY CURRENT vs. TEMPERATURE
DS1087L toc01
ACTIVE SUPPLY CURRENT vs. VOLTAGE
DS1087L toc02
SUPPLY CURRENT vs. PRESCALER
OUTPUT UNLOADED 6 5 CURRENT (mA) 4 3 2 1 0 3.6V 3.3V 2.7V
DS1087L toc03
7.5 VCC = 3.3V FREQUENCY = 66.6MHz OE = PDN = VCC 15pF LOAD
8.0 7.0 6.0 CURRENT (mA) 5.0 4.0 3.0 2.0 1.0 FREQUENCY = 66.6MHz OUTPUT UNLOADED OE = PDN = VCC
7
7.0 CURRENT (mA)
6.5
6.0 8.2pF LOAD 4.7pF LOAD UNLOADED -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 TEMPERATURE (C)
5.5
5.0
0 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 VOLTAGE (V)
1
10
100
1000
PRESCALER (DECIMAL)
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3.3V Spread-Spectrum EconOscillator DS1087L
Typical Operating Characteristics
(VCC = 3.3V, TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. TEMPERATURE WITH OE = 0
DS1087L toc04 DS1087L toc05
SUPPLY CURRENT vs. PRESCALER
6 5 CURRENT (mA) 4 3 -40C, +25C, +85C 2 1 0 1 10 100 1000 PRESCALER (DECIMAL) VCC = 3.3V OUPUT UNLOADED 4.0 3.5 3.0 CURRENT (mA) 2.5 2.0 1.5
SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE
1.8 1.6 1.4 CURRENT (A) VCC = 3.3V OUTPUT UNLOADED
DS1087L toc06
2.0
VCC = 2.7V OUTPUT UNLOADED
FREQUENCY = 66.6MHz
1.2 1.0 0.8 0.6 0.4 0.2 0
FREQUENCY = 206.4kHz 1.0 0.5 0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 TEMPERATURE (C)
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 TEMPERATURE (C)
FREQUENCY % CHANGE vs. SUPPLY VOLTAGE
DS1087L toc07
FREQUENCY % CHANGE vs. TEMPERATURE
DS1087L toc08
ACTIVE SUPPLY CURRENT vs. SCL FREQUENCY
VCC = SDA = 3.3V FREQUENCY = 66.6MHz OUTPUT UNLOADED
DS1087L toc09
1.00 FREQUENCY % CHANGE (FROM 3.3V) 0.80 0.60 0.40 0.20 0 -0.20 -0.40 -0.60 -0.80 -1.00 OUTPUT LOADED WITH 12pF OSCILLOSCOPE PROBE FREQUENCY = 66.6MHz
1.50 FREQUENCY % CHANGE (FROM 25C) 1.00 0.50 0 -0.50 -1.00 -1.50 VCC = 3.3V FREQUENCY = 66.6MHz OUTPUT LOADED WITH 12pF OSCILLOSCOPE PROBE
7 6 SUPPLY CURRENT (mA) 5 4 3 2 1 0
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 VOLTAGE (V)
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 TEMPERATURE (C)
0
100
200
300
400
SCL FREQUENCY (kHz)
DUTY CYCLE vs. VOLTAGE
DS1087L toc10
DUTY CYCLE vs. TEMPERATURE
59 58 DUTY CYCLE (%) 57 56 55 54 53 52 51 50 VCC = 3.3V FREQUENCY = 66.6MHz OUTPUT LOADED WITH 12pF OSCILLOSCOPE PROBE
DS1087L toc11
60 59 58 DUTY CYCLE (%) 57 56 55 54 53 52 51 50 FREQUENCY = 66.6MHz TA = +25C OUTPUT LOADED WITH 12pF OSCILLOSCOPE PROBE
60
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 VOLTAGE (V)
0
10
20
30
40
50
60
70
TEMPERATURE (C)
6
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3.3V Spread-Spectrum EconOscillator
Pin Description
PIN 1 2 3 4 5 6 7 8 NAME OUT SPRD VCC GND OE PDN SDA SCL Oscillator Output Dither Enable. When the pin is high, the dither is enabled. When the pin is low, the dither is disabled. Power Supply Ground Output Enable. When the pin is high, the output buffer is enabled. When the pin is low, the output is disabled but the internal master oscillator is still on. Power-Down. When the pin is high, the master oscillator is enabled. When the pin is low, the master oscillator is disabled (power-down mode). 2-Wire Serial Data. This pin is for serial data transfer to and from the device. 2-Wire Serial Clock. This pin is used to clock data into and out of the device. FUNCTION
DS1087L
VCC SDA SCL 2-WIRE INTERFACE
EEPROM CONTROL REGISTERS ADDR PRESCALER
DS1087L
PDN
FACTORY-PROGRAMMED OSCILLATOR MASTER OSCILLATOR OUTPUT PRESCALER BY 1, 2, 4...256 OUT
DITHER CONTROL
OE SPRD GND TRIANGLE WAVE GENERATOR
DITHER SIGNAL
Figure 1. Functional Diagram _____________________________________________________________________ 7
3.3V Spread-Spectrum EconOscillator DS1087L
Table 1. Register Summary
REGISTER PRESCALER ADDR WRITE EE ADDR 02h 0Dh 3Fh X1 X1 X1 X1 LO/ HIZ X1 BINARY J0 X1 P3 WC P2 A2 P1 A1 P0 A0 FACTORY DEFAULT 110- - - - - b 11110000b -- ACCESS R/W R/W --
No Data
X1 = Don't care; read as one.
Detailed Description
A block diagram of the DS1087L is shown in Figure 1.
programmed frequency. Although the output frequency changes when the dither is enabled, the duty cycle does not change. The dither is controlled by the J0 bit in the PRESCALER register and enabled with the SPRD pin. The maximum spectral attenuation occurs when the prescaler is set to 1. The spectral attenuation is reduced by 2.7dB for every factor of 2 that is used in the prescaler. This happens because the prescaler's divider function tends to average the dither in creating the lower frequency. However, the most stringent spectral emission limits are imposed on the higher frequencies where the prescaler is set to a low divider ratio. A triangle-wave generator injects an offset element into the master oscillator to dither its output. The dither rate (see Equation 1) is based on the master oscillator frequency. Figure 2 shows a plot of the output frequency versus dither rate. Dither Rate = f0 4096 (1)
Output Frequency
The internal master oscillator can generate a square wave with a frequency range of 33.3MHz to 66.6MHz. The master oscillator frequency and output frequency are factory programmed, although the user can use the programmable divider to divide the master oscillator frequency by 2x (where x equals 0 to 8).
Output Control and Power-Down
Two user control signals control the output. The outputenable pin, OE, gates the clock output buffer and the PDN pin disables the master oscillator and turns off the output for power-sensitive applications (note: the power-down command must persist for at least two output frequency cycles plus 10s for deglitching purposes). On power-up, the output is disabled until power is stable and the master oscillator has generated 512 clock cycles. Both controls feature a synchronous enable, which ensures there are no output glitches when the output is enabled. The synchronous enable also ensures a constant time interval (for a given frequency setting) from an enable signal to the first output transition.
where f0 = master oscillator frequency
Register Summary
The DS1087L registers are used to change the dither amount, output frequency, and slave address. A summary of the registers is shown in Table 1. Once programmed into EEPROM, the settings only need to be reprogrammed if it is desired to reconfigure the device.
Spread Spectrum
The DS1087L can reduce radiated emission peaks. The output frequency can be dithered 2% or 4% below the
OUTPUT FREQUENCY
PRESCALER Register
Bit 5: Output Low or High-Z. The LO/HIZ bit controls the output. During power-down, while the output is deactivated, if the LO/HIZ bit is set to 0, the output is high-Z. If the LO/HIZ bit is set to 1, the output is driven low. Dither Control. The J0 bit controls the dither applied to the output. When J0 is high, 2% peak dither is selected. When J0 is low, 4% peak dither is selected.
fO/N
(fO/N) - 4% 0 fO/4096
DITHER RATE 2fO/4096
Bit 4:
WHERE N = (2X) f0 = FACTORY PROGRAMMED MASTER OSCILLATOR FREQUENCY
Figure 2. Output Frequency vs. Dither Rate 8
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3.3V Spread-Spectrum EconOscillator
Bits 3 to 0: Prescaler Divider. The prescaler bits (bits P3 to P0) divide the master oscillator frequency by 2x where x can be from 0 to 8. Any prescaler bit value entered that is greater than 8 decodes as 8. Write Control. The WC bit determines if the EEPROM is to be written to after register contents have been changed. If WC = 0 (default), EEPROM is written automatically after a write. If WC = 1, the EEPROM is only written when the WRITE EE command is issued. See the WRITE EE Command section for more information. Address. The A0, A1, A2 bits determine the lower nibble of the 2-wire slave address.
_______2-Wire Serial Port Operation
2-Wire Serial Data Bus
The DS1087L communicates through a 2-wire serial interface. A device that sends data onto the bus is defined as a transmitter, and a device receiving data as a receiver. The device that controls the message is called a "master." The devices that are controlled by the master are "slaves." A master device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions must control the bus. The DS1087L operates as a slave on the 2-wire bus. Connections to the bus are made through the open-drain I/O lines SDA and SCL. The following bus protocol has been defined (see Figures 3 and 5): * * Data transfer can be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH are interpreted as control signals.
DS1087L
ADDR Register
Bit 3:
Bits 2 to 0:
WRITE EE Command
The WRITE EE command is useful in closed-loop applications where the registers are frequently written. In applications where the register contents are frequently written, the WC bit should be set to 1 to prevent wearing out the EEPROM. Regardless of the value of the WC bit, the value of the ADDR register is always written immediately to EEPROM. When the WRITE EE command has been received, the contents of the registers are copied into the EEPROM, thus locking in the register settings.
Accordingly, the following bus conditions have been defined: Bus not busy: Both data and clock lines remain HIGH. Start data transfer: A change in the state of the data line, from HIGH to LOW, while the clock is HIGH, defines a START condition. Stop data transfer: A change in the state of the data line, from LOW to HIGH, while the clock line is HIGH, defines the STOP condition.
SDA
MSB SLAVE ADDRESS R/W DIRECTION BIT ACKNOWLEDGEMENT SIGNAL FROM RECEIVER SCL 1 START CONDITION 2 6 7 8 9 ACK REPEATED IF MORE BYTES ARE TRANSFERRED 1 2 3-7 8 9 ACK STOP CONDITION OR REPEATED START CONDITION ACKNOWLEDGEMENT SIGNAL FROM RECEIVER
Figure 3. 2-Wire Data Transfer Protocol _____________________________________________________________________ 9
3.3V Spread-Spectrum EconOscillator
MSB 1 0 1 1 A2 A1 A0 LSB R/W
Figure 4. Slave Address
Data valid: The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data bytes transferred between START and STOP conditions is not limited, and is determined by the master device. The information is transferred byte-wise and each receiver acknowledges with a ninth bit. Within the bus specifications a standard mode (100kHz clock rate) and a fast mode (400kHz clock rate) are defined. The DS1087L works in both modes. Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the byte has been received. The master device must generate an extra clock pulse that is associated with this acknowledge bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge-related clock pulse. Of course, setup and hold times must be taken into account. When the DS1087L EEPROM is being written to, it is not able to perform additional responses. In this case, the slave DS1087L sends a not acknowledge to any data transfer request made by the master. It resumes normal operation when the EEPROM operation is complete. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition.
RE A
D/W
RIT
DEVICE IDENTIFIER
DEVICE ADDRESS
Figures 3, 4, 5, and 6 detail how data transfer is accomplished on the 2-wire bus. Depending upon the state of the R/W bit, two types of data transfer are possible: 1) Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the slave address. Next follows a number of data bytes. The slave returns an acknowledge bit after each received byte. 2) Data transfer from a slave transmitter to a master receiver. The first byte (the slave address) is transmitted by the master. The slave then returns an acknowledge bit. Next follows a number of data bytes transmitted by the slave to the master. The master returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received byte, a not acknowledge is returned. The master device generates all the serial clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or with a repeated START condition. Since a repeated START condition is also the beginning of the next serial transfer, the bus is not released. The DS1087L can operate in the following two modes: Slave receiver mode: Serial data and clock are received through SDA and SCL. After each byte is received, an acknowledge bit is transmitted. START and STOP conditions are recognized as the beginning and end of a serial transfer. Address recognition is performed by hardware after reception of the slave address and direction bit. Slave transmitter mode: The first byte is received and handled as in the slave receiver mode. However, in this mode, the direction bit indicates that the transfer direction is reversed. Serial data is transmitted on SDA by the DS1087L while the serial clock is input on SCL. START and STOP conditions are recognized as the beginning and end of a serial transfer.
DS1087L
EB
IT
Slave Address
Figure 4 shows the first byte sent to the device. It includes the device identifier, device address, and the R/W bit. The device address must match the address set in the ADDR register (bits A0, A1, and A2).
Registers/Commands
See Table 1 for the complete list of registers/commands and Figure 6 for an example of using them.
10
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3.3V Spread-Spectrum EconOscillator DS1087L
SDA
tBUF tLOW tR tF
tHD:STA
tSP
SCL tHD:STA STOP START tHD:DAT tHIGH tSU:DAT REPEATED START tSU:STA tSU:STO
Figure 5. 2-Wire AC Characteristics
TYPICAL 2-WIRE WRITE TRANSACTION MSB START 1 0 1 1 LSB A2* A1* A0* R/W DEVICE ADDRESS READ/ WRITE SLAVE ACK MSB b7 b6 b5 b4 b3 b2 b1 LSB b0 SLAVE ACK MSB b7 b6 b5 b4 b3 b2 b1 LSB b0 SLAVE ACK STOP
DEVICE IDENTIFIER
COMMAND/REGISTER ADDRESS
DATA
EXAMPLE 2-WIRE TRANSACTIONS (WHEN A0, A1, AND A2 ARE ZERO) B0h 02h DATA SLAVE SLAVE A) SINGLE BYTE WRITE 10000000 START 1 0 1 1 0 0 0 0 ACK 0 0 0 0 0 0 1 0 ACK -WRITE PRESCALER REGISTER TO 128 B0h B) SINGLE BYTE READ -READ PRESCALER REGISTER START 1 0 1 1 0 0 0 0 02h SLAVE SLAVE 00000010 ACK ACK REPEATED START
SLAVE ACK B1h
STOP
10110001
DATA MASTER SLAVE 10000000 NACK ACK
STOP
*THE ADDRESS DETERMINED BY A0, A1, AND A2 MUST MATCH THE ADDRESS SET IN THE ADDR REGISTER.
Figure 6. 2-Wire Transactions
Application Information
Power-Supply Decoupling
To achieve the best results when using the DS1087L, decouple the power supply with 0.01F and 0.1F high-quality, ceramic, surface-mount capacitors. Surface-mount components minimize lead inductance, which improves performance, and ceramic capacitors tend to have adequate high-frequency response for
decoupling applications. These capacitors should be placed as close to the VCC and GND pins as possible.
Stand-alone Mode
SCL and SDA cannot be left floating even in standalone mode. If the DS1087L never needs to be programmed in-circuit, including during production testing, SDA and SCL can be wired high.
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11
3.3V Spread-Spectrum EconOscillator DS1087L
Typical Operating Circuits
Processor-Controlled Mode
VCC MICROPROCESSOR DITHERED 130kHz TO 66.6MHz OUTPUT VCC OUT SPRD VCC GND DECOUPLING CAPACITORS (0.1F and 0.01F) 4.7k SCL SDA 4.7k XTL1/OSC1 XTL2/OSC2 VCC 2-WIRE INTERFACE N.C. DITHERED 130kHz TO 66.6MHz OUTPUT VCC OUT SPRD VCC GND DECOUPLING CAPACITORS (0.1F and 0.01F) *SDA AND SCL CAN BE CONNECTED DIRECTLY HIGH IF THE DS1087L NEVER NEEDS TO BE PROGRAMMED IN-CIRCUIT, INCLUDING DURING PRODUCTION TESTING. SCL*
Stand-Alone Mode
VCC
DS1087L
SDA* PDN OE
DS1087L
PDN OE
Chip Topology
TRANSISTOR COUNT: 10000 SUBSTRATE CONNECTED TO GROUND
Package Information
For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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